Designing RNS and QRNS full adder based converters

A systematic graph-based methodology for designing optimal VLSI RNS (Residue Number System) converters from binary system to RNS to quadratic RNS (QRNS) and conversely, using full adders as the basic building block is introduced. The design methodology derives array architectures starting from the algorithm level and ending up with the bit level design. This methodology can be considered as a unified methodology, since all fundamental steps can be applied to all types of the proposed converters. Finally, the derived architectures can be used as the processing element of a regular array architecture. The derived architectures are implemented into two-dimensional regular array processor and characterized by small hardware and area-time complexity, and throughput rate, compared with existing implementations.